Reference: http://www.fpga-faq.org/archives/68350.html

Article: 68363
Subject: Re: Can't do a single byte read in Nios?
From: kempaj@yahoo.com (Jesse Kempa)
Date: 2 Apr 2004 17:57:35 -0800
Links: << >>  << T >>  << A >>

"Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<106p5chij03th48@news.supernews.com>...
> Hello,
> 
> I'm having a problem reading a single one byte register on a Nios/Cyclone
> board.  I've seen this on the devkit board as well.  Every time I read a
> single memory location, the Nios is automatically generating reads for the
> next 3 locations as well.
> 
> This causes bad things to happen when you are reading a location that is
> within 3 bytes of a location that does not want to be read.
> 
> There doesn't appear to be a setting in the SOPC User Logic GUI.  Is there a
> .ptf file entry I can edit to stop this behavior?
> 
> The UL has 5 address bits, 8 databits, (RD#,WR#,CS#) and is an Avalon Memory
> Slave.
> 
> Thanks,
> Ken

Ken,

Others have explained what is going on, but there are some subtle
changes that can be made to your system to get the behavior you want.
When you add your peripheral, I am presuming you are using the
'interface to user logic' wizard. If so, be sure you're selecting
"Avalon Register Slave" (as opposed to memory slave).

In the case of a 32-bit master, this has the effect right-shifting the
address bus going to the slave by two bits (this does not occur if you
are going through a tri-state bus bridge.. you can do so on your own
by connecting address line A2 from Nios to A0 on your peripheral
manually). The Avalon reference manual describes this in more detail.

The reasoning behind this feature is to cover this very case -- where
register access to a peripheral of a 'strange' width may upset other
registers that happen to be inadvertently accessed. It also allows a
peripheral to have a register that is 1 bit wide, followed by one that
is 5 bits, or 30 bits, etc. With this, a master can then read *or
write* a peripheral register of any bit width (up to the master's
width) by presenting a word-aligned address (0, 4, 8...). On the slave
side, the corresponding registers are decoded as 0..1..2... (again,
the above example is based on a 32-bit wide master).

One last note: Turning this feature on turns *off* the dynamic bus
sizing feature of Avalon.

Hope this is of some help to your design.

Regards,

Jesse Kempa
Altera Corp.
jkempa at altera dot com