THIS IS AN ARCHIVED PAGE
Originally created by Denny Chao
Slightly modified by Victor Liu
SoPC Digital Oscilloscope Section
Notes
- Here's a 5x7 dot matrix character pattern file in C.
- Don't ignore timing warnings as they may introduce sporadic errors which are hard to debug.
- Ways to fix timing warnings:
- insert FF in long combinational logic chains
- use same edge of clock to clock the FF's
- slow down system clock
- When programming in Nios assembly, avoid using %r#, use %i#, %l#, %o#, and %g# instead.
- SoPC Builder may give error with no specified address bus in user interface logic.
- After completing an assembly function, remove from STUBFNCS.C.
- To make standalone, can use PLD to program FPGA.
- Alternatives for programming logic: ABEL, PALASM (both are outside FPGA).
- When designing VRAM state machine, beware of back to back timings.
- The VRAM's power pin locations are opposite of what you'd usually expect.
- Link containing assembler directive listings
here.
- Software files should be located in /cpu_sdk/...
- SignalTap Embedded Logic Analyzer.
- OK to ignore compiler warnings in regards to 'STATIC' usage in Glen's code.
Use nios-build ... --cc "-D FLAT_MEMORY" ... to get rid of FAR pointer complaints.- Simulate design in blocks.
- Quartus simulation tool:
- create vector waveform file
- generate functional simulation netlist for functional simulation
- analyze project before running timing simulation
- Can use VHDL for simple logic equations.
- Can use makefile example to compile your project.
- Signal Probe feature: brings internal signals to i/o pins.
- Signal Tap feature: embedded logic analyzer.
- Op-amp circuits.
- This file talks about the
GNU debugger Insight in more details.
- Other tutorials can be found under \altera\kits\nios\documents.
- Use 2 hold states in your SRAM/ROM timings under SoPC builder.
- The external ROM's name under SoPC builder should not contain "ROM".
- Consider using a counter to check address lines to external memory.
- Tristate unused pins under Quartus.
- Don't use the EP20K200 compatibility I/O pins (see
schematic).
- APEX20k device pin-out
- FPGA Connections
- nCONFIG pulled high
- nSTATUS pulled high
- CONFDONE pulled high
- nCE grounded
- xTDI tied to TDI
- xTDO tied to TDO
- Nios Assembly
- register window
- input, local, output, control, global, K registers
- branch delay slot
- code segment declaration: ".text"
- data segment declaration: ".data"
- variable declaration: "var1: .space WORD"
- excalibur.s, nios_macros.s, nios_setup.s, ...
- custom instructions
- 32-bit Nios Processor!
- Beware that the FPGA board pins are swapped by the adapter board.
- Change '.qsf' file to reflect EP20K100QC208-3V (example
file [ln 193])
- Check for shorts between PWR and GND!
- Use wire-wrap wires as leads on your continuity checker.
- SRAM testing: can write a short program to test it.
- ROM testing: program using BP programmer then read with Nios.
- Go over the Nios software reference manuals
- Order or sample your A/D chip!
- The flash ROM we provide is wider than normal DIP's.
- Check out the Do's and Don't's page.
- Solder corners of the surface mount chip first.
- Flip the chip and put flux on the bottom of the pins before placing on the pad.
- When using wick, apply solder to the iron, if not coming off, apply more.
- You need to show TAs you can solder surface mounts before getting FPGAs from us.
- Can use Protel, Powerpoint, Paint, Microsoft Visio to draw timing diagrams.
- Draw worst case scenarios for timing.
- If you're not sure of the chip you're using, use the slowest one.
- One bypass capacitor for each chip.
- Need test points.
- Check for shorts between PWR and GND after adding new sections.
- Byblaster: Parallel port -> JTAG for programming FPGA.
- GERMS: add serial port to Nios and chip on the prototype board.
- Serial chips: MAX232, MC145405 etc (need to purchase from stock room).
- Use 32-bit Nios processor for larger address space.
- Use Nios v3.2 (not Nios II).
- May want to use gdb over GERMS.
- The following tutorial is useful.
- Construct additional hardware blocks either by using Quartus library components (gates, counters...)
or by writing VHDL.
- Hardware interface code need to be written in Nios assembly.
- The menu is supplied to you. You can change it in C/C++ or assembly.
- Download datasheets and manuals from Altera.
- FPGA Part #: EP20K100QC208-3V (APEX20K family)
- 5x protel library can be downloaded from
here.
- Use 32MHz clock box.
- Byte = 8 bits, half-word = 16 bits, word = 32 bits.
- Remember oftentimes you can sample chips for free with free shipping.
Analog Devices provides free next day shipping!
- You can obtain Quartus from Chris's ftp server, instructions found here.
Datasheets
A/D chips we supply
- MC10319
- 25 MHz, 8-bit parallel flash A/D converter
(external circuitry needed to meet 0-3V input requirement)
- AD770?
- Fast A/D converter w/ ECL output (external transistor circuitry needed)
Parts we supply
- Am7202A
- First-In First-Out (FIFO) 1024 x 9-bit CMOS Memory
For other datasheets please visit the course website.
Miscellaneous Documents
Board layout of old 52 protoboard
Useful Links
Sites to obtain datasheets or order parts
Major chip manufacturers
Useful Websites